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TYPICAL APPLICATIONS
SELECTING SEMICONDUCTORS
? I D should be higher than,
Input Protection P-MOSFET
? V DSS should be at least 1.5 times V IN ? V DSS ≥ 1.5 x
21.6 V = 32.4 V.
? I D should be higher than I OUT /(1-D) ? I D ≥ 1.67 A
? The pulsed drain current capability of the MOSFET
I OUT
1 ? D
? I D ≥ 1.67 + 0.33 = 2.0 A
+
Δ I
2
should be of several tens of amps due to the inrush
current. If this current causes serious problems to the
transistor during turn on, a small capacitor of
approximately 100 nF can be placed in parallel with the
triggering resistor RG1, to minimize and smooth such
an effect.
Switching Diode
? V RRM should be at least 1.2 times than V OUT ? V RRM ≥
1.2 x 39 V ≈ 47 V.
? I F-AV should be higher than,
+
As this transistor will be on at all times, the power
dissipation must be considered (I D2 x R DS-ON ), as well as the
thermal dissipation pad.
Switching MOSFET
I OUT
1 ? D
? I F-AV ≥ 1.67 + 0.33 = 2.0 A
Δ I
2
? V DSS should be at least 1.5 times V OUT + V D ? V DSS ≥
1.5 x (39 V + 0.7 V) ≈ 60 V
PCB LAYOUT RECOMMENDATIONS
LAYOUT HINTS AND TIPS
? Connect the exposed pad of the IC to the ground planes of
the board using as many vias as possible. These ground
planes must be as large as possible to dissipate the heat
from the IC.
? All references pins, i.e. PGND, AGND and DGND must be
connected together. Their corresponding ground planes
must be joined together with as many vias as possible.
? Try to place all components on just one Layer.
? When tracing differential pairs, it is advisable:
? to know that routing between planes eliminates the
potential for coupling external noise.
? to route other signals al least 5 h (microstrip) or 4 h
(stripline) away from the differential pairs.
? to know that is it not essential to route them together, if
the traces are inner layered and have the same length.
? to design a PCB with 4 or more layers in order to get
better results on the impedances of the traces
(referenced to a next layer ground plane), as well as to
minimize capacitive and inductive cross talk between
layers. As a result, the following PCB layer stacking is
suggested [3] :
Ground
Signal/Power
Signal/Power
Ground
Signal/Poured
Ground
Ground
Signal/Poured
Power
Signal/Ground
Power
Ground
Signal/Power
Ground
Signal/Power
Ground
Signal/Power
Ground
Power
Signal/Ground
Figure 25. Recommended PCB Layer Stacking.
? Never trace the Feedback and Control signals like CS,
REFERENCES
COMP, SLEW, GD and OVP close to the switching node.
[1]
MANIKTALA, Sanjaya. Switching Power Supplies A to
ERICKSON, Robert W and MAKSIMOVIC, Dragan.
? Make sure that each of the channel traces are capable of
handling the LED currents. As a directly proportional
reference, a 10 mils trace with a thickness of 1.0 oz/ft 2 is
capable of handling one ampere.
Z. US: Newnes, 2006.
[2]
Fundamentals of Power Electronics , Second Edition,
University of Colorado.
[3] HARTLEY, Rick. Signal Integrity and EMI Control in
High Speed Circuits and PCBs. US: Lectures notes for
Freescale Semiconductor Mexico presentation,2008.
34848
Analog Integrated Circuit Device Data
Freescale Semiconductor
33
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